1. Field of the Invention
The present invention relates to a digital circuit, and more particularly, to a logic circuit combining an exclusive OR gate and an exclusive NOR gate.
2. Description of the Related Art
FIG. 1A is a circuit diagram of a conventional exclusive OR gate 100. The exclusive OR gate 100 exclusively ORs a first input signal A and a second input signal B and outputs an output signal Y. The exclusive OR gate 100 includes two branches 110 and 120 between a power supply voltage Vdd and a ground voltage Vss. The first branch 110 includes first and second PMOS transistors 101 and 102 and first and second NMOS transistors 103 and 104, which are connected in series between the power supply voltage Vdd and the ground voltage Vss. The second branch 120 includes third and fourth PMOS transistors 105 and 106 and third and fourth NMOS transistors 107 and 108, which are connected in series between the power supply voltage Vdd and the ground voltage Vss. The drains of the respective second and fourth PMOS transistors 102 and 106 and first and third NMOS transistors 103 and 107 are connected, thereby generating the output signal Y.
The gate of the first PMOS transistor 101 is connected to the second input signal B. The gate of the second PMOS transistor 102 is connected to an inverted first input signal Ā. The gate of the first NMOS transistor 103 is connected to the first input signal A. The gate of the second NMOS transistor 104 is connected to the second input signal B. The gate of the third PMOS transistor 105 is connected to an inverted second input signal B. The gate of the fourth PMOS transistor 106 is connected to the first input signal A. The gate of the third NMOS transistor 107 is connected to the inverted first input signal Ā. The gate of the fourth NMOS transistor 108 is connected to the inverted second input signal B.
When the first input signal A and the second input signal B are at the same logic level, the exclusive OR gate 100 generates a logic “0”. When the first input signal A and the second input signal B are at different logic levels, the exclusive OR gate 100 generates a logic “1”. Such operation is illustrated in a truth table shown in FIG. 1B.
FIG. 2A is a circuit diagram of a conventional exclusive NOR gate 200. The exclusive NOR gate 200 has the same structure as the exclusive OR gate 100 shown in FIG. 1A but has different connections of the first and second input signals A and B than the exclusive OR gate 100. In detail, the gate of the first PMOS transistor 101 is connected to the second input signal B. The gate of the second PMOS transistor 102 is connected to the first input signal A. The gate of the first NMOS transistor 103 is connected to the inverted first input signal Ā. The gate of the second NMOS transistor 104 is connected to the second input signal B. The gate of the third PMOS transistor 105 is connected to the inverted second input signal B. The gate of the fourth PMOS transistor 106 is connected to the inverted first input signal Ā. The gate of the third NMOS transistor 107 is connected to the first input signal A. The gate of the fourth NMOS transistor 108 is connected to the inverted second input signal B.
When the first input signal A and the second input signal B are at the same logic level, the exclusive NOR gate 200 generates a logic “1”. When the first input signal A and the second input signal B are at different logic levels, the exclusive OR gate 100 generates a logic “0”. Such operation is illustrated in a truth table shown in FIG. 2B.
FIG. 3 is a circuit diagram of another conventional exclusive OR gate 300. The exclusive OR gate 300 includes first and second PMOS transistors 301 and 302 connected in series between a first input signal A and a second input signal B, first and second NMOS transistors 303 and 304 connected in series between the first input signal A and an inverted second input signal B, and an inverter 305. The inverter 305 receives the second input signal B and outputs the inverted second input signal B. The gate of the first PMOS transistor 301 is connected to the second input signal B. The gate of the second PMOS transistor 302 is connected to the first input signal A. The gate of the first NMOS transistor 303 is connected to the inverted second input signal B. The gate of the second NMOS transistor 304 is connected to the first input signal A. The drains of the respective first and second PMOS transistors 301 and 302 and of the respective first and second NMOS transistors 303 and 304 are connected, thereby generating an output signal Y. A truth table for the exclusive OR gate 300 is the same as that shown in FIG. 1B.
FIG. 4 is a circuit diagram of another conventional exclusive NOR gate 400. The exclusive NOR gate 400 has the same structure as the exclusive OR gate 300, with the exception that PMOS transistors are exchanged with the NMOS transistors. In detail, the exclusive NOR gate 400 includes first and second NMOS transistors 401 and 402 connected in series between the first input signal A and the second input signal B, first and second PMOS transistors 403 and 404 connected in series between the first input signal A and the inverted second input signal B, and an inverter 405. The inverter 405 receives the second input signal B and outputs the inverted second input signal B. The gate of the first NMOS transistor 401 is connected to the second input signal B. The gate of the second NMOS transistor 402 is connected to the first input signal A. The gate of the first PMOS transistor 403 is connected to the inverted second input signal B. The gate of the second PMOS transistor 404 is connected to the first input signal A. The drains of the respective first and second NMOS transistors 401 and 402 and of the first and second PMOS transistors 403 and 404 are connected, thereby generating an output signal Y. A truth table for the exclusive NOR gate 400 is the same as that shown in FIG. 2B.
As described above, the exclusive OR gates 100 or 300 and the exclusive NOR gates 200 or 400 can be implemented from each other by changing the connection of input signals or changing the arrangement of transistors.
However, to implement both an exclusive OR gate and an exclusive NOR gate, two circuits are needed. If both an exclusive OR gate and an exclusive NOR gate can be implemented using a single circuit, use of a digital circuit can be extended. Accordingly, a logic circuit combining an exclusive OR gate and an exclusive NOR gate is desired.